1. Field of the Invention
The present invention relates to a technique for processing single and double precision floating point numbers and, more particularly, to a technique for encoding multiple floating point formats into a "common" double precision floating point format in a way that allows a single precision arithmetic logic unit to be built on top of a double precision arithmetic logic unit while minimizing the hardware requirements for supporting multiple formats.
2. Description of the Prior Art
Recently, floating point processors have been designed which allow concurrent execution of a floating point multiply, divide, add and load or store instructions, thereby significantly increasing the processing efficiency of a floating point processor. For example, DeLano et al. describe in an article entitled "A High Speed Superscalar PA-RISC Processor", Proceedings of the Compcon Spring 1992, Digest of Papers, San Francisco, CA, Feb. 24-28, 1992, a central processing unit comprising an integer processor and a floating point coprocessor which achieves exceptional performance and structural density. The floating point coprocessor consists of a register file, a floating point ALU, a floating point multiplier, and a floating point divide/square root unit and is integrated onto the same chip as the integer processor. Dynamic logic was used to exploit the speed and density characteristics of such circuits using a system of self-timed logic.
Floating point coprocessors of the type described by DeLano et al. typically comprise either single precision (i.e., operating on 32-bit operands) or double precision (i.e., operating on 64-bit operands) processing units. As is well known to those skilled in the art, single and double precision binary floating point numbers are typically formatted to have three fields: a sign bit, s; several exponent bits, e; and several fraction or mantissa bits, f. In accordance with the standard IEEE twos complement floating point format, the bits of the floating point numbers are arranged such that the most significant bit is the sign bit s, the next most significant bits are the exponent bits e, and the least significant bits represent the mantissa f. Numbers in such floating point formats may either be normalized numbers, denormalized numbers, infinity, zero, or some other non-numerical value. However, each representable non-zero numerical value typically has just one encoding.
Prior art floating point processors contain 32 or 64-bit data registers which the floating point instructions use as operands. Software of the floating point processors accesses these data registers with single or double word load and store instructions. Each of the floating point data registers may contain values in a number of different formats.
Conventionally, floating point processing units perform double precision operations using single precision (i.e., 32-bit) data paths, whereby two iterations through the floating point units are required to compute a result in a double precision format. For example, for double precision addition the two double precision operands A and B are respectively stored in two consecutive single precision storage locations. If the exponent of operand A is greater than the exponent of operand B (e.sub.a &gt;e.sub.b), then operand A is loaded into concatenated registers A.sub.HIGH (most significant word) and A.sub.LOW (least significant word). The fraction is shifted right with corresponding increments to e.sub.a until e.sub.a =e.sub.b. The least significant word of operand B is loaded into another register, register B, and the sum A.sub.LOW +B is formed and stored in register A.sub.LOW. The carry bit is saved. Then, the remaining mantissa bits of operand B are loaded into register B. The sum of A.sub.HIGH +B+Carry is formed and stored in register A.sub.HIGH. The sum is the concatenation of A.sub.HIGH and A.sub.LOW, and the sum can be normalized by shifting left and rounding or truncating.
Previously, integrated circuit process technology has not provided the device density necessary to implement a 64-bit arithmetic data path on the same chip as the integer processor. However, recent advances in integrated circuit technology now make this possible. Because of this breakthrough, it is now possible to integrate a double precision floating point unit onto the same chip as the integer processor so as to achieve a high level of double precision performance. However, at the same time, it is desired to also support high single precision performance with minimal hardware requirements to support arithmetic in multiple data formats. The present invention has been designed to meet this need.